Readable Verilog Generator
Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis.
Install
npx skills add Eriemon/verilog-generator --skill readable-verilog-generatorgit clone --depth 1 https://github.com/Eriemon/verilog-generator.git /tmp/verilog-generator
mkdir -p ~/.claude/skills
cp -r /tmp/verilog-generator/. ~/.claude/skills/readable-verilog-generatorPersonal skills live in ~/.claude/skills. Use .claude/skills in a project folder to share a skill with your team.
From the SKILL.md
# Readable Verilog Generator Generate, analyze, improve, and verify readable Verilog-2001 RTL through the bundled runtime under `scripts/python/`. Keep design RTL and verification testbenches in `.v` files, use `scripts/python/facade/verilog_api.py` for host integration, and treat formatter-AST and external-tool evidence as stronger than model self-assessment. ## Route - `create/write`: confirm the design contract, then use `requirements -> codegen_plan -> spec_document -> python -> rtl`. - `deep_review`: insert a non-empty structured review between the Python semantic model and RTL; it must cover interface, reset, timing/pipeline, handshake or FSM behavior, width, synthesis, testbench coverage, and risks. - `review/analyze`: remain read-only and report the eight public gate states before suggesting changes. - `annotate`: preserve an immutable normalized baseline, change only `//` comments, prove token equivalence from that baseline, and rerun the final deliverable gate. - `repair/refactor`: bind the task to real RTL, reproduce or validate the issue, and apply the smallest evidence-backed change. - `agentic_repair`: use the existing-RTL `verify_existing_verilog(...)` loop with an explicit `conservative`, `semi_auto`, or `auto_apply` choice. - `validate`: collect static or external evidence without implicitly editing RTL.
Details
- Skill name
readable-verilog-generator- Repository
- Eriemon/verilog-generator
- License
- Apache-2.0
- Repo updated
- 25 August 2026
FAQ
What does the Readable Verilog Generator skill do?
Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis.
How do I install the Readable Verilog Generator skill?
skills CLI (Claude Code, Cursor, Codex and more): npx skills add Eriemon/verilog-generator --skill readable-verilog-generator. Skills go in ~/.claude/skills (personal) or .claude/skills (project), and Claude loads them automatically when a task matches the description.
Is Readable Verilog Generator popular?
It lives in Eriemon/verilog-generator, which has 326 GitHub stars and 23 forks.
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