Fpga Hardware Design and Review Guide
Comprehensive FPGA hardware design guide based on real-world project experience. Covers pipeline architecture, timing optimization, SystemVerilog coding patterns, CDC handling, and practical debugging techniques. Use this skill when: (1) designing FPGA modules with timing constraints, (2) implementing video processing or data path designs, (3) optimizing for resource utilization and timing closure, (4) reviewing RTL code for hardware implementation, (5) debugging synthesis or implementation issues.
Install
npx skills add cobbpeng/fpga-hardware-design-and-review-guide --skill fpga-hardware-design-and-review-guidegit clone --depth 1 https://github.com/cobbpeng/fpga-hardware-design-and-review-guide.git /tmp/fpga-hardware-design-and-review-guide
mkdir -p ~/.claude/skills
cp -r /tmp/fpga-hardware-design-and-review-guide/. ~/.claude/skills/fpga-hardware-design-and-review-guidePersonal skills live in ~/.claude/skills. Use .claude/skills in a project folder to share a skill with your team.
From the SKILL.md
# FPGA Hardware Design Guide A practical FPGA hardware design guide based on real-world project experience. ## Core Design Philosophy ### 1. Pipeline Architecture First When processing high-speed data streams (video, network packets), adopt multi-stage pipeline design: - **Single-stage processing**: Combinational logic delay too large, prone to timing violations - **Multi-stage pipeline**: Insert registers at each stage, distribute delay, increase clock frequency - **Typical applications**: RGB-to-YUV conversion, image filtering, protocol parsing **Real Case**: RGB-to-YUV converter with 5-stage pipeline - Stage 0: Input register (synchronize input signals) - Stage 1: Multiply operation (coefficient * pixel value) - Stage 2: Partial accumulation (R*coef_r + G*coef_g) - Stage 3: Final accumulation (+ B*coef_b) - Stage 4: Shift and saturation (truncate result to 8-bit) ### 2. The Art of Bit-Width Management **Bit-width calculation principles**: ``` Multiplication bit-width = input bit-width + coefficient bit-width + 1 (sign bit) Accumulation bit-width = multiplication bit-width + log2(number of additions) + 1 (guard bit) ``` **Rules of thumb**: - 8-bit unsigned * 9-bit signed coefficient = 18-bit signed result - 3 numbers of 18-bit addition = 20-bit (leave 2 guard bits to prevent overflow) - After right-shifting 8 bits = 8-bit final result ### 3. Iron Rules of Synchronous Design **Rules that must be followed**:
Details
- Skill name
fpga-hardware-design-and-review-guide- License
- MIT
- Repo updated
- 6 February 2026
FAQ
What does the Fpga Hardware Design and Review Guide skill do?
Comprehensive FPGA hardware design guide based on real-world project experience. Covers pipeline architecture, timing optimization, SystemVerilog coding patterns, CDC handling, and practical debugging techniques. Use this skill when: (1) designing FPGA modules with timing constraints, (2) implementing video processing or data path designs, (3) optimizing for resource utilization and timing closure, (4) reviewing RTL code for hardware implementation, (5) debugging synthesis or implementation issues.
How do I install the Fpga Hardware Design and Review Guide skill?
skills CLI (Claude Code, Cursor, Codex and more): npx skills add cobbpeng/fpga-hardware-design-and-review-guide --skill fpga-hardware-design-and-review-guide. Skills go in ~/.claude/skills (personal) or .claude/skills (project), and Claude loads them automatically when a task matches the description.
Is Fpga Hardware Design and Review Guide popular?
It lives in cobbpeng/fpga-hardware-design-and-review-guide, which has 20 GitHub stars and 2 forks.
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